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2–16
Table 2–1. Generated Files (Part 1 of 2)
Filename
<variation name> .bsf
<variation name> . html
<variation name> .vo or .vho
<variation name> .v or .vhd
<variation name> _bb.v
(Note 1) (2)
Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Description
Quartus II symbol file for the MegaCore function variation. You
can use this file in the Quartus II block diagram editor.
MegaCore function report file.
VHDL or Verilog HDL IP functional simulation model.
A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the
Quartus II software.
Verilog HDL black-box file for the MegaCore function variation.
Use this file when using a third-party EDA tool to synthesize
your design.
<variation name> _auk_ddr_clk_gen.v or .vhd
<variation name> _auk_ddr_datapath.v or .vhd
<variation name> _auk_ddr_datapath_pack.v or .vhd
<variation name> _auk_ddr_dll.v or .vhd
<variation name> _auk_ddr_dqs_group.v or .vhd
<variation name> _auk_ddr_sdram.v or .vhd
<variation name> _ddr_sdram_vsim.tcl
<variation name> _example_driver.v or .vhd
<variation name> _example_settings.txt
<variation name> .qip
<variation name> .v or .vhd (1)
add_constraints_for_ <variation name> .tcl
altera_vhdl_support.vhd
auto_add_ddr_constraints.tcl
auto_verify_ddr_timing_constraints.tcl
constraints_out.txt
ddr_lib_path.tcl
ddr_pll_fb_stratixii.v or .vhd
ddr_pll_ <device name> .v or .vhd
generic_ddr_dimm_model.vhd
generic_ddr_sdram.vhd
generic_ddr2_sdram.vhd
DDR and DDR2 SDRAM Controller Compiler User Guide
Design file that contains the clock output generators.
Design file that instantiates the byte groups and the clock output
generators.
A VHDL package, which contains a component that the IP
functional simulation model uses.
Optional design file that instantiates the Stratix or Stratix II DLL
(Stratix series only).
Design file that contains the datapath byte groups.
Design file that instantiates the controller logic and the datapath
The ModelSim simulation script.
The example driver.
The settings file for your variation, which the add constraints
and the verify timing scripts use.
Contains Quartus II project information for your MegaCore
function variations.
Example design file.
The add constraints script for the variation.
A VHDL package that contains functions for the generated
entities. This file may be shared between MegaCore functions.
The add constraints script, which calls the variation-specific add
constraints scripts.
The auto verify timing script, which calls the variation-specific
verify timing scripts.
Log file that IP Toolbench creates while generating the add
constraints script.
The Tcl library path file.
Design file for the Stratix II fedback PLL.
Design file for the system PLL.
VHDL simulation file.
VHDL simulation file.
VHDL simulation file.
? March 2009 Altera Corporation
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